The present invention relates to the manufacturing of computer chips, and in particular to chip design optimization, and to a method for developing an electronic chip circuit layout having a plurality of signal source latches and logic, wherein an initial logic is defined by a synthesis step, and during a chip layout generation procedure which processes said synthesized logic, a timing-driven placement for placing cloned latches on said circuit layout is run based on timing data stored for each sink in a database accessible during the method.